Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2124

Datasheet

14

0b

RW/1C

This bit is set by the Intel PCH whenever it signals 

SERR# (internally). The SERR_EN bit (bit 8 in the Command Register) must be 1 for this 

bit to be set. See error handling section for complete list of conditions handled. Software 

clears this bit by writing a 1 to this bit location.

Core

13

0b

RW/1C

This bit is set when XHC, as a master, 

receives a master-abort status on a memory access. This is treated as a Host Error and 

halts the DMA engines. Software clears this bit by writing a 1 to this bit location.

Core

12

0b

RW/1C

This bit is set when XHC, as a master, receives 

a target abort status on a memory access. This is treated as a Host Error and halts the 

DMA engines. Software clears this bit by writing a 1 to this bit location.

Core

11

0b

RW/1C

This bit is used to indicate when the XHC 

function responds to a cycle with a target abort.

Core

10:9

01b

RO

This 2-bit field defines the timing for DEVSEL# 

assertion. Read-Only.

Core

8

0b

RW/1C

This bit is set by the Intel PCH 

whenever a data parity error is detected on a XHC read completion packet on the 

internal interface to the XHC host controller and bit 6 of the Command register is set to 

1. Software clears this bit by writing a 1 to this bit location.

Core

7

1b

RO

Reserved as 1 Read-Only.

Core

6

0b

RO

Reserved as 0. Read-Only.

Core

5

0b

RO

Reserved as 0. Read-Only.

Core

4

1b

RO

Hardwired to 1 indicating that offset 34h contains a valid 

capabilities pointer.

Core

3

0b

RO/V

This read-only bit reflects the state of this function's interrupt 

at the input of the enable/disable logic. This bit is a 1 when the interrupt is asserted. 

This bit will be 0 when the interrupt is deasserted. The value reported in this bit is 

independent of the value in the Interrupt Enable bit.

Core

2:0

000b

RO

Reserved.

Core