Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2126
Datasheet
18.6.8
Base Class Code (BCC)—Offset Bh
Access Method
Default: 0Ch
18.6.9
Master Latency Timer (MLT)—Offset Dh
Access Method
Default: 00h
18.6.10
Header Type (HT)—Offset Eh
Access Method
Default: 00h
Bit
Range
Default &
Access
Field Name (ID): Description
7:0
03h
RO
Sub Class Code (SCC):
A value of 03h indicates that this is a Universal Serial Bus Host
Controller.
Power Well:
Core
Type:
PCI Configuration Register
(Size: 8 bits)
Offset:
7
4
0
0
0
0
0
1
1
0
0
BC
C
Bit
Range
Default &
Access
Field Name (ID): Description
7:0
0Ch
RO
Base Class Code (BCC):
A value of 0Ch indicates that this is a Serial Bus controller.
Power Well:
Core
Type:
PCI Configuration Register
(Size: 8 bits)
Offset:
7
4
0
0
0
0
0
0
0
0
0
ML
T
Bit
Range
Default &
Access
Field Name (ID): Description
7:0
00h
RO
Master Latency Timer (MLT):
Because the XHC controller is internally implemented
with arbitration on an internal interface, it does not need a master latency timer. The
bits will be fixed at 0.
Power Well:
Core
Type:
PCI Configuration Register
(Size: 8 bits)
Offset: