Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
2129
18.6.14
Capabilities Pointer (CAP_PTR)—Offset 34h
Access Method
Default: 70h
18.6.15
Interrupt Line (ILINE)—Offset 3Ch
Access Method
Default: 00h
18.6.16
Interrupt Pin (IPIN)—Offset 3Dh
Access Method
Default: 00h
Type: 
PCI Configuration Register
(Size: 8 bits)
Offset: 
7
4
0
0
1
1
1
0
0
0
0
CA
P_PTR
Bit 
Range
Default & 
Access
Field Name (ID): Description
7:0
70h
RO
Capabilities Pointer (CAP_PTR): 
This register points to the starting offset of the 
capabilities ranges.
Power Well: 
Core
Type: 
PCI Configuration Register
(Size: 8 bits)
Offset: 
7
4
0
0
0
0
0
0
0
0
0
ILINE
Bit 
Range
Default & 
Access
Field Name (ID): Description
7:0
00h
RW
Interrupt Line (ILINE): 
This data is not used by the Intel PCH. It is used as a 
scratchpad register to communicate to software the interrupt line that the interrupt pin 
is connected to.
Power Well: 
Core
Type: 
PCI Configuration Register
(Size: 8 bits)
Offset: 
7
4
0
0
0
0
0
0
0
0
0
IP
IN