Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2130

Datasheet

Default: 000000FDh

7:0

00h

RO/V

Bits 3:0 reflect the value programmed in the interrupt pin 

registers in chipset configuration space. Bits 7:4 are hardwired to 0000b. See Chap 6 for 

value.

Core

PCI Configuration Register

(Size: 32 bits)

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1

A

CCTRL

EC

O1

RM

TA

S

E

RR

URD

URRE

IIL1E

XH

CIL1E

D3IL1E

PC

PWT

SW

AXH

C

I

L23HRA

WC

UT

A

G

CP

UD

A

G

CNP

UD

A

G

CCP

UD

AG

C

31

0b

RW/O

This bit is used by BIOS to lock/unlock lockable bits. When 

set to '1' the write access to bits locked by this bit is disabled (locked state). When set 

to '0', the write access to bit locked by this bit is enabled (unlocked state). Writable once 

after platform reset.

Core

30:25

00h

RW

ECO bits are used during silicon bringup for FIBing. NOT for EDS

Core

24

0b

RW

When set, it allows the out-of-band error 

reporting from the xHCI Controller to be reported as SERR# (if SERR# reporting is 

enabled) and thus set the STS.SSE bit.

Core

23

0b

RW/C

Set the HW when xHCI Controller received 

an unsupported request posted cycle. Cleared by SW when the bit is written with value 

of '1'.

Core

22

0b

RW

When set this bit allows the URD bit 

to be reported as SERR# (if SERR# reporting is enabled) and thus set the STS.SSE bit.

Core

21:19

000b

RW

If programmed to non-zero, it allows L1 

power managed to be enabled after the time-out period specified. 000: Disabled 001: 

32 bb_cclk 010: 64 bb_cclk 011: 128 bb_cclk 100: 256 bb_cclk 101: 512 bb_cclk 110: 

1024 bb_cclk 111: 131072 bb_cclk

Core