Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2132
Datasheet
Default: 0003C000h
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
O
CCFG
D
O
N
E
EC
O1
DREQ
BCC
IDMA_RDREQSZ
CTRL
XH
CUPRDRO
E
IOSFS
R
AD
UNP
PA
SW
AXH
C
IP
RA
WDD
WAW
D
E
SW
AC
XIH
B
SW
AD
MIL
1
IH
B
L1FP
2CGW
C
RD
REQS
Z
C
TRL
Bit
Range
Default &
Access
Field Name (ID): Description
31
0b
RW/O
OC Configuration Done (OCCFGDONE):
This bit is used by BIOS to prevent spurious
switching during OC configuration. Any write this register bit will cause it to set. It must
be set by BIOS after configuration of the OC mapping bits is complete. Once this bit is
set, OC mapping shall not be changed by SW.
Power Well:
SUS
30:26
00h
RW
ECO1:
NOT for EDS ECO bits are used during silicon bringup for FIBing.
Power Well:
Core
25
0b
RW
DMA Request Boundary Crossing Control (DREQBCC):
This bit controls the
boundary crossing limit of each Read/Write Request. 0: 4KB 1: 64B
Power Well:
Core
24:22
0h
RW
IDMA Read Request Size Control (IDMA_RDREQSZCTRL):
Read Request Size
Control: This bit controls the maximum size of each Read Request. 000: 128B 001:
256B 011 - 110: Reserved 111: 64B
Power Well:
Core
21
0b
RW
XHC Upstream Read Relaxed Ordering Enable (XHCUPRDROE):
This policy
controls the Relaxed Ordering attribute for upstream reads. 0 - xHC will clear RO for all
upstream read requests. 1 - xHC will set RO for all upstream read requests.
Power Well:
Core
20
0b
RW
IOSF Sideband Register Access Disable (IOSFSRAD):
When set, it disables the
IOSF sideband interface from accepting any host space register access.
Power Well:
Core
19:14
0Fh
RW
Upstream Non-Posted Pre-Allocation (UNPPA):
This field reserves data sizes, in 64
byte chunks, of the downstream completion resource. This value is zero based. 000000
- 111111: Pre-allocate 64 bytes - 4096 bytes If set greater than the default allows over-
allocation If set less than default allows under-allocation Only allowed to be
programmed when BME = 0 and no outstanding downstream completion
Power Well:
Core