Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
2134
Datasheet
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0
Rsvd
2
NU
EFBCG
PS
SRA
M
PG
TE
N
SSL
S
E
U
S
B2PLLSE
IOSFST
C
G
E
HS
TC
GE
SS
TC
G
E
XH
CIGE
U3S
XH
CF
TC
LK
S
E
XHCBB
TC
G
IPISO
XH
CH
ST
CGU
2
NRWE
XH
CUSB
2
PLLS
DLE
H
S
UXDMIPLLSE
S
S
PLLSUE
XH
CBL
C
GE
HS
LT
C
G
E
SS
LT
C
G
E
IOSFB
TC
G
E
IOSFBL
C
G
E
Bit 
Range
Default & 
Access
Field Name (ID): Description
31:29
0h
RO
Rsvd2: 
Reserved
Power Well: 
Core
28
0b
RW
Nak’ing USB2.0 EPs for Backbone Clock Gating and PLL Shutdown 
(NUEFBCGPS): 
This field controls whether Naking USB2.0 EPs, once in Naking low 
priority schedule, should be considered as active for the considerations for backbone 
clock gating and PLL shutdown or not. 0: Naking USB2.0 EPs are not considered to be 
active for Backbone Clock Gating and PLL Shutdown evaluation. 1: Naking USB2.0 EPs 
are considered to be active for Backbone clock gating and PLL shutdown evaluation.
Power Well: 
Core
27
0b
RW
SRAM Power Gate Enable (SRAMPGTEN): 
This register enables the SRAM Power 
Gating when PLL shutdown conditions for all clock domains have been met 0 - Disallow 
SRAM Power Gating. 1 - Allow SRAM Power Gating
Power Well: 
Core
26
0h
RW
SS Link PLL Shutdown Enable (SSLSE): 
This register enables the SS P3 state to be 
exposed to PXP PLL Shutdown conditions on behalf of all USB SS Ports ontop of trunk 
clock gating. 0 - P3 state NOT allowed to result in PXP PLL shutdown. 1- P3 state 
allowed to result in PXP PLL shutdown
Power Well: 
Core
25
0h
RW
USB2 PLL Shutdown Enable (USB2PLLSE): 
When set, this bit allows USB2 PLL to be 
shutdown when HS Link trunk clock is gated, and xHC can tolerate PLL spin up time for 
subsequent clock request. Note: if USB2 PLL Shutdown Disable Fuse is '1', hardware will 
always see '0' as an output from this register. BIOS reading this register should always 
return the correct value.
Power Well: 
Core
24
0h
RW
IOSF Sideband Trunk Clock Gating Enable (IOSFSTCGE): 
When set, this bit allows 
the IOSF sideband clock trunk to be gated when idle conditions are met.
Power Well: 
Core
23:20
0h
RW
HS Backbone PXP Trunk Clock Gate Enable (HSTCGE): 
This register determines 
the HS Ux state(s) which will be exposed to Backbone PXP trunk gating of core clock. Uy 
is a state allowed to result in trunk gating when ss_tcg_ux_en(x) is asserted. (0) ==) 
U0 or deeper (1) ==) NA (no support for U1) (2) ==) U2 (L1) or deeper (3) ==) U3 
(L2) or deeper
Power Well: 
Core