Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2139
Default: 01h
18.6.25
Next Item Pointer #1 (PM_NEXT)—Offset 71h
This register is modified and maintained by BIOS
Access Method
Default: 80h
18.6.26
Power Management Capabilities (PM_CAP)—Offset 72h
Normally, this register is read-only to report capabilities to the power management
software. In order to report different power management capabilities depending on the
system in which the Intel PCH is used, the write access to this register is controlled by
the Access Control bit (ACCTRL). The value written to this register does not affect the
hardware other than changing the value returned during a read. This register is
modified and maintained by BIOS
Access Method
Type:
PCI Configuration Register
(Size: 8 bits)
Offset:
7
4
0
0
0
0
0
0
0
0
1
PM
_CID
Bit
Range
Default &
Access
Field Name (ID): Description
7:0
01h
RO
PCI Power Management Capability ID (PM_CID):
A value of 01h indicates that this
is a PCI Power Management capabilities field.
Power Well:
Core
Type:
PCI Configuration Register
(Size: 8 bits)
Offset:
7
4
0
1
0
0
0
0
0
0
0
PM_NE
X
T
Bit
Range
Default &
Access
Field Name (ID): Description
7:0
80h
RW/L
Next Item Pointer #1 (PM_NEXT):
This register defaults to 80h, which indicates that
the next capability registers begin at configuration offset 80h. This register is writable
when the Access Control bit is set to '0'. This allows BIOS to effectively hide the next
capability registers, if necessary. This register should only be written during system
initialization before the plug-and-play software has enabled any master-initiated traffic.
Values of: 80h implies next capability is MSI 00h implies that MSI capability is hidden.
Note: This value is never expected to be programmed.
Power Well:
Core