Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2140
Datasheet
Default: C1C2h
18.6.27
Power Management Control/Status (PM_CS)—Offset 74h
Access Method
Default: 0008h
Type:
PCI Configuration Register
(Size: 16 bits)
Offset:
15
12
8
4
0
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
PME
_
S
u
p
p
ort
D2_Su
p
port
D1_Su
p
port
A
u
x_Cu
rre
nt
DSI
RS
VD
PM
EC
lo
ck
Ve
rs
io
n
Bit
Range
Default &
Access
Field Name (ID): Description
15:11
11000b
RW/L
PME_Support:
This 5-bit field indicates the power states in which the function may
assert PME#. The Intel PCH XHC does not support the D1 or D2 states. For all other
states, the Intel PCH XHC is capable of generating PME#. Software should never need to
modify this field. NOT for EDS: However, the ability to change this field may prove useful
for some systems.
Power Well:
Core
10
0b
RW/L
D2_Support:
The D2 state is not supported.
Power Well:
Core
9
0b
RW/L
D1_Support:
The D1 state is not supported.
Power Well:
Core
8:6
111b
RW/L
Aux_Current:
The Intel PCH XHC reports 375mA maximum Suspend well current
required when in the D3cold state. This value can be written by BIOS when a more
accurate value is known.
Power Well:
Core
5
0b
RW/L
DSI:
The Intel PCH reports 0, indicating that no device-specific initialization is required.
Power Well:
Core
4
0b
RO
Reserved (RSVD):
Reserved.
Power Well:
Core
3
0b
RW/L
PME Clock (PMEClock):
The Intel PCH reports 0, indicating that no PCI clock is
required to generate PME#.
Power Well:
Core
2:0
010b
RW/L
Version:
The Intel PCH reports 010, indicating that it complies with Revision 1.1 of the
PCI Power Management Specification.
Power Well:
Core
Type:
PCI Configuration Register
(Size: 16 bits)
Offset: