Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2141
18.6.28
Message Signaled Interrupt CID (MSI_CID)—Offset 80h
Access Method
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
PM
E_
S
ta
tus
Data_S
cale
Dat
a_Sele
ct
PM
E_En
RSVD
NSR
RSVD
2
Po
we
rS
tate
Bit
Range
Default &
Access
Field Name (ID): Description
15
0b
RW/1C
PME_Status:
This bit is set when the Intel PCH XHC would normally assert the PME#
signal independent of the state of the PME_En bit. Writing a 1 to this bit will clear it and
cause the internal PME to deassert (if enabled). Writing a 0 has no effect. This bit must
be explicitly cleared by the operating system each time the operating system is loaded.
Power Well:
SUS
14:13
00b
RO
Data_Scale:
The Intel PCH hardwires these bits to 00 because it does not support the
associated Data register.
Power Well:
Core
12:9
0h
RO
Data_Select:
The Intel PCH hardwires these bits to 0000 because it does not support
the associated Data register.
Power Well:
Core
8
0b
RW
PME_En:
A 1 enables the Intel PCH XHC to generate an internal PME signal when
PME_Status is 1. This bit must be explicitly cleared by the operating system each time it
is initially loaded.
Power Well:
SUS
7:4
0h
RO
Reserved (RSVD):
Reserved.
Power Well:
Core
3
1b
RO
No Soft Reset (NSR):
), this bit indicates that devices transitioning from D3hot to D0
because of PowerState commands do not perform an internal reset. Configuration
Context is preserved. Upon transition from the D3hot to the D0 Initialized state, no
additional operating system intervention is required to preserve Configuration Context
beyond writing the PowerState bits. Transition from D3hot to D0 by a system or bus
segment reset will return to the device state D0 Uninitialized with only PME context
preserved if PME is supported and enabled.
Power Well:
Core
2
0b
RO
Reserved (RSVD2):
Reserved.
Power Well:
Core
1:0
00b
RW
PowerState:
This 2-bit field is used both to determine the current power state of XHC
function and to set a new power state. The definition of the field values are: 00b - D0
state 11b - D3hot state If software attempts to write a value of 10b or 01b in to this
field, the write operation must complete normally, however, the data is discarded and no
state change occurs. When in the D3hot state, the Intel PCH must not accept accesses
to the XHC memory range, but the configuration space must still be accessible.
Power Well:
Core