Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2143
18.6.31
Message Signaled Interrupt Message Address (MSI_MAD)—
Offset 84h
Access Method
Default: 00000000h
18.6.32
Message Signaled Interrupt Upper Address (MSI_MUAD)—
Offset 88h
Access Method
8
0b
RO
Per-Vector Masking Capable (PVM):
Specifies whether controller supports MSI per
vector masking. Not supported
Power Well:
Core
7
1b
RO
64 Bit Address Capable (C64):
Specifies whether capable of generating 64-bit
messages. This device is 64-bit capable.
Power Well:
Core
6:4
0h
RW
Multiple Message Enable (MME):
Indicates the number of messages the controller
should assert. This device supports multiple message MSI.
Power Well:
Core
3:1
011b
RO
Multiple Message Capable (MMC):
Indicates the number of messages the controller
wishes to assert. This field must be set by HW to reflect the number of Interrupters
supported. Encoding number of Vectors requested (number of Interrupters) 000 1 001 2
010 4 011 8 100 16 101 32 110-111 Reserved
Power Well:
Core
0
0b
RW
MSI Enable (MSIE):
If set to 1, MSI is enabled and the traditional interrupt pins are
not used to generate interrupts. If cleared to 0, MSI operation is disabled and the
traditional interrupt pins are used.
Power Well:
Core
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Add
r
RS
VD
Bit
Range
Default &
Access
Field Name (ID): Description
31:2
00000000h
RW
Addr:
Lower DW of system specified message address, always DWORD aligned
Power Well:
Core
1:0
00b
RO
Reserved (RSVD):
Reserved.
Power Well:
Core