Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2145
18.6.35
High Speed Configuration 2 (HSCFG2)—Offset A4h
Access Method
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
EC
O1
Rsvd
1
HS
AAP
E
PA
PE
EC
O2
EN_HSIC_
B
U
S_ST
A
T
E
_
TO
_BUS_RE
S
ET
EN_H
S
IC_CNC
T
_
D
IS
CNC
T
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0000h
RW
ECO bits Core (ECO1):
ECO bits are used during silicon bringup for FIBing.
Power Well:
Core
15:10
00h
RO
Rsvd1:
Reserved.
Power Well:
Core
9
0h
RW
xHC HS Async Active Propogation Enable (HSAAPE):
This register controls the hs
async active exposusre to PMC via the xHC active indication 0 HS Async Active is not
propogated to PMC 1 HS Async Active is propogated to PMC
Power Well:
Core
8
1h
RW
xHC Periodic Active Propogation Enable (PAPE):
This register controls the periodic
active exposusre to PMC via the xHC active indication 0 Periodic Active is not propogated
to PMC 1 Periodic Active is propogated to PMC
Power Well:
Core
7:2
00h
RW
ECO bits SUS (ECO2):
ECO bits are used during silicon bringup for FIBing.
Power Well:
SUS
1
0h
RW
EN_HSIC_BUS_STATE_TO_BUS_RESET:
Disable VLV2 C0 Fix: Port Power OFF
triggering the HSIC BUS State to BUS RESET 0 = VLV2 C0 Fix [DEFAULT] 1 = Revert
back to VLV2 B2 functionality
Power Well:
SUS
0
0h
RW
EN_HSIC_CNCT_DISCNCT:
Disable VLV2 C0 Fix: Port Power OFF triggering the HSIC
Internal Connect Flag to clear. This will enable Disconnect-Connect capability for HSIC I/
F. 0 = VLV2 C0 Fix [DEFAULT] 1 = Revert back to VLV2 B2 functionality
Power Well:
SUS
Type:
PCI Configuration Register
(Size: 32 bits)
Offset: