Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2150
Datasheet
18.6.39
XHCI USB3 Overcurrent Pin Mapping 1 (U3OCM1)—Offset C8h
The RW/L property of this register is controlled by OCCFDONE bit.
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rsvd
1
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
00000000h
RO
Rsvd1:
Reserved
Power Well:
Core
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rsvd
1
OC
4M
Rsvd
2
OC
3M
Rsvd
3
OC
2M
Rsvd
4
OC
1M
Bit
Range
Default &
Access
Field Name (ID): Description
31:25
00h
RO
Rsvd1:
Reserved.
Power Well:
Core
24
0b
RW/L
OC4 Mapping (OC4M):
Each bit position maps OC4 to a set of ports as follows: The
OC4 pin is ganged to the overcurrent signal of each port that has its corresponding bit
set. It is SW's responsibility to ensure that a given port's bit map is set only for one OC
pin. Bit 27 26 25 24 Port 4 3 2 1
Power Well:
SUS
23:17
00h
RO
Rsvd2:
Reserved.
Power Well:
Core
16
0b
RW/L
OC3 Mapping (OC3M):
Each bit position maps OC3 to a set of ports as follows: The
OC3 pin is ganged to the overcurrent signal of each port that has its corresponding bit
set. It is SW's responsibility to ensure that a given port's bit map is set only for one OC
pin. Bit 19 18 17 16 Port 4 3 2 1
Power Well:
SUS
15:9
00h
RO
Rsvd3:
Reserved.
Power Well:
Core