Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2152

Datasheet

Default: 00000000h

16

0b

RW/L

Each bit position maps OC7 to a set of ports as follows: The 

OC7 pin is ganged to the overcurrent signal of each port that has its corresponding bit 

set. It is SW's responsibility to e nsure that a given port's bit map is set only for one OC 

pin. Bit 16 Port 1

SUS

15:9

00h

RO

Reserved.

Core

8

0b

RW/L

Each bit position maps OC6 to a set of ports as follows: The 

OC6 pin is ganged to the overcurrent signal of each port that has its corresponding bit 

set. It is SW's responsibility to e nsure that a given port's bit map is set only for one OC 

pin. Bit 8 Port 1

SUS

7:1

00h

RO

Reserved.

Core

0

0b

RW/L

Each bit position maps OC5 to a set of ports as follows: The 

OC5 pin is ganged to the overcurrent signal of each port that has its corresponding bit 

set. It is SW's responsibility to e nsure that a given port's bit map is set only for one OC 

pin Bit 0 Port 1

SUS

PCI Configuration Register

(Size: 32 bits)

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Rsvd1

US

B2HCS

E

L

31:9

000000h

RO

Reserved.

Core

8:0

000h

RW

This field maps the USB2 port between the XHCI 

and EHCI controller (it has no effect on USB3). When set to 1, Routes USB2 pins to the 

XHCI controller. Routes OC pin to XHCI (based on the mapping in the OC register). 

Masks the USB2 port from the EHCI. Masks OC pin from ECHI. When set to 0, Routes all 

the USB2 pins to the legacy EHCI. Routes OC pin to EHCI (based on the mapping in the 

OC register). Masks the USB2 port from the XHCI. Masks OC pin from XHCI. Port to bit 

mapping is in one-hot encoding, i.e. bit 0 controls port 1 and so on.

SUS