Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2152
Datasheet
18.6.41
USB2 Port Routing (USB2PR)—Offset D0h
Access Method
Default: 00000000h
16
0b
RW/L
OC7 Mapping (OC7M):
Each bit position maps OC7 to a set of ports as follows: The
OC7 pin is ganged to the overcurrent signal of each port that has its corresponding bit
set. It is SW's responsibility to e nsure that a given port's bit map is set only for one OC
pin. Bit 16 Port 1
Power Well:
SUS
15:9
00h
RO
Rsvd3:
Reserved.
Power Well:
Core
8
0b
RW/L
OC6 Mapping (OC6M):
Each bit position maps OC6 to a set of ports as follows: The
OC6 pin is ganged to the overcurrent signal of each port that has its corresponding bit
set. It is SW's responsibility to e nsure that a given port's bit map is set only for one OC
pin. Bit 8 Port 1
Power Well:
SUS
7:1
00h
RO
Rsvd4:
Reserved.
Power Well:
Core
0
0b
RW/L
OC5 Mapping (OC5M):
Each bit position maps OC5 to a set of ports as follows: The
OC5 pin is ganged to the overcurrent signal of each port that has its corresponding bit
set. It is SW's responsibility to e nsure that a given port's bit map is set only for one OC
pin Bit 0 Port 1
Power Well:
SUS
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rsvd1
US
B2HCS
E
L
Bit
Range
Default &
Access
Field Name (ID): Description
31:9
000000h
RO
Rsvd1:
Reserved.
Power Well:
Core
8:0
000h
RW
USB2 HC Selector (USB2HCSEL):
This field maps the USB2 port between the XHCI
and EHCI controller (it has no effect on USB3). When set to 1, Routes USB2 pins to the
XHCI controller. Routes OC pin to XHCI (based on the mapping in the OC register).
Masks the USB2 port from the EHCI. Masks OC pin from ECHI. When set to 0, Routes all
the USB2 pins to the legacy EHCI. Routes OC pin to EHCI (based on the mapping in the
OC register). Masks the USB2 port from the XHCI. Masks OC pin from XHCI. Port to bit
mapping is in one-hot encoding, i.e. bit 0 controls port 1 and so on.
Power Well:
SUS