Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2153
18.6.42
USB2 Port Routing Mask (USB2PRM)—Offset D4h
The RW/L property of this register is controlled by the ACCTRL bit.
Access Method
Default: 00000000h
18.6.43
USB3 Port Routing (USB3PR)—Offset D8h
Access Method
Default: 00000000h
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rsvd
1
US
B
2
HC
SE
LM
Bit
Range
Default &
Access
Field Name (ID): Description
31:9
000000h
RO
Rsvd1:
Reserved.
Power Well:
Core
8:0
000h
RW/L
USB2 HC Selector Mask (USB2HCSELM):
This field allows the BIOS to communicate
to the OS which USB 2.0 ports can be switched from the EHCI controller to the xHCI
controller. When set to 1, The OS may switch the USB 2.0 port between the EHCI and
xHCI host controllers by modifying the corresponding USB2HCSEL bit. When set to 0,
The OS shall not modify the corresponding USB2HCSEL bit. BIOS shall set this bit to a
'1' if the corresponding USB2HCSEL bit is RW, unless it knows an internal USB 2.0 device
attached to that port will not work under xHCI. Port to bit mapping is in one-hot
encoding, i.e. bit 0 controls port 1 and so on.
Power Well:
Core
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rs
vd1
US
B3S
S
EN
Bit
Range
Default &
Access
Field Name (ID): Description
31:4
0000000h
RO
Rsvd1:
Reserved.
Power Well:
Core