Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2158
Datasheet
18.6.49
DFT 1 (DFT1)—Offset F0h
Not for EDS
Access Method
Default: 00000000h
5:4
01b
RW
FS/LS Stagger Offset for USB2 Port 3 (FSLSPS3):
FS/LS Stagger Offset for USB2
Port 3 00: No time offset / Staggering disabled 01: 4ns time offset 10: 8ns time offset
11: 12ns time offset
Power Well:
Core
3:2
10b
RW
FS/LS Stagger Offser for USB2 Port 2 (FSLSPS2):
FS/LS Stagger Offset for USB2
Port 2 00: No time offset / Staggering disabled 01: 4ns time offset 10: 8ns time offset
11: 12ns time offset
Power Well:
Core
1:0
00b
RW
FS/LS Stagger Offset for USB2 Port 1 (FSLSPS1):
FS/LS Stagger Offset for USB2
Port 1 00: No time offset / Staggering disabled 01: 4ns time offset 10: 8ns time offset
11: 12ns time offset
Power Well:
Core
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SS
D
FTC
R
C
Rsvd
1
SS
D
FT
LM
S
E
L
SS
D
FTC
R
C
S
E
L
SS
D
FT
C
P
S
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0000h
RO
Super Speed DFT CRC (SSDFTCRC):
These register bits contain the value of Super
Speed DFT CRC
Power Well:
Core
15:8
00h
RO
Rsvd1:
Reserved.
Power Well:
Core
7
0h
RW
Super Speed DFT LFPS Mode Select (SSDFTLMSEL):
This bit selects the Super
Speed DFT LFPS mode, and will only take effect when Super Speed HBP mode is
enabled. 0b: HBP logic will internally loopback TX LFPS as RX LFPS and AFE RX LFPS
path to the controller is disconnected. 1b: RX LFPS path works normally
Power Well:
Core