Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2160

Datasheet

Not for EDS

Default: 00000F00h

11:8

0h

RW

Number of repeatable fixed pattern within a 

packet Note: Connect register bit 3 to counter bit 7, register bit 2 to counter bit 5, 

register bit 1 to counter bit 3, register bit 0 to counter bit 1. Counter bits 6, 4, 2 and 0 

will be tied off to 0. Hence, the programmable loop number shall be: 0000b: 0 loop 

0001b: 2 loops 0010b: 8 loops 0011b: 10 loops 1100b: 160 loops 1101b: 162 loops 

1110b: 168 loops 1111b: 170 loops (max)

Core

7:6

0h

RW

Operational Mode in test mode. These 

signals select between various operational modes: 00b: Normal Operation 01b: Non-

Driving 10b: Disable Bit Stuffing and NRZI encoding 11b: Reserved

Core

5

0h

RW

Termination Select in test mode. This signal 

selects between the FS and HS terminations: 0b: HS termination enabled 1b: FS 

termination enabled

Core

4:3

0h

RW

Transceiver Select in test mode. This 

signal selects between the LS, FS and HS transceivers: 00b: HS transceiver enabled 

01b: FS transceiver enabled 10b: LS transceiver enabled 11b: Reserved

Core

2:1

0h

RO

Loopback Status for port selected by 

UTMIDFTPS 00b: Reset condition 01b: Comparator has started receiving data and the 

received data matches with the TX pattern. 10b: Comparator has started receiving data 

the received data does not match with the TX pattern but there was no assertion of RC 

error from UTMI. 11b: Comparator has started receiving data and RX ERROR was 

asserted for at least one clock by UTMI. Note that this does not reflect the status of 

pattern comparison since RX error from UTMI is unexpected for loopback.

Core

0

0h

RW

Enable loopback test mode. If asserted, loopback 

test mode is enabled

Core

PCI Configuration Register

(Size: 32 bits)

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0

Rsvd

DPID

SID

MNFR

PPID