Intel E3815 FH8065301567411 Data Sheet

Intel

Product codes

FH8065301567411

Intel

®

Atom™ Processor E3800 Product Family

2164

Datasheet

4BC–4BFh

4

“Port X Hardware LPM Control Register (PORTHLPM4)—Offset 4BCh” on

00000000h

4C0–4C3h

4

“Port 8 Status and Control USB2 (PORTSC5USB2)—Offset 4C0h” on

000002A0h

4C4–4C7h

4

“Port 5 Power Management Status and Control USB2

(PORTPMSC5USB2)—Offset 4C4h” on page 2204

00000000h

4CC–4CFh

4

“Port X Hardware LPM Control Register (PORTHLPM5)—Offset 4CCh” on

00000000h

4D0–4D3h

4

“Port 6 Status and Control USB2 (PORTSC6USB2)—Offset 4D0h” on

000002A0h

4D4–4D7h

4

“Port 6 Power Management Status and Control USB2

(PORTPMSC6USB2)—Offset 4D4h” on page 2208

00000000h

4DC–4DFh

4

“Port X Hardware LPM Control Register (PORTHLPM6)—Offset 4DCh”

00000000h

4E0–4E3h

4

“Port 1 Status and Control USB3 (PORTSC1USB3)—Offset 4E0h” on

000002A0h

4E4–4E7h

4

“Port 1 Power Management Status and Control USB3

(PORTPMSC1USB3)—Offset 4E4h” on page 2211

00000000h

4E8–4EBh

4

“Port 1 Link Info (PORTLI1)—Offset 4E8h” on page 2212

00000000h

2000–2003h

4

“Microframe Index (MFINDEX)—Offset 2000h” on page 2213

00000000h

2020–2023h

4

“Interrupter 1 Management (IMAN1)—Offset 2020h” on page 2213

00000000h

2024–2027h

4

“Interrupter 1 Moderation (IMOD1)—Offset 2024h” on page 2214

00000FA0h

2028–202Bh

4

“Event Ring Segment Table Size 1 (ERSTSZ1)—Offset 2028h” on

00000000h

2030–2033h

4

“Event Ring Segment Table Base Address Low 1 (ERSTBA_LO1)—

Offset 2030h” on page 2215

00000000h

2034–2037h

4

“Event Ring Segment Table Base Address High 1 (ERSTBA_HI1)—

Offset 2034h” on page 2216

00000000h

2038–203Bh

4

“Event Ring Dequeue Pointer Low 1 (ERDP_LO1)—Offset 2038h” on

00000000h

203C–203Fh

4

“Event Ring Dequeue Pointer High 1 (ERDP_HI1)—Offset 203Ch” on

00000000h

2040–2043h

4

“Interrupter 2 Management (IMAN2)—Offset 2040h” on page 2217

00000000h

2044–2047h

4

“Interrupter 2 Moderation (IMOD2)—Offset 2044h” on page 2218

00000FA0h

2048–204Bh

4

“Event Ring Segment Table Size 2 (ERSTSZ2)—Offset 2048h” on

00000000h

2050–2053h

4

“Event Ring Segment Table Base Address Low 2 (ERSTBA_LO2)—

Offset 2050h” on page 2219

00000000h

2054–2057h

4

“Event Ring Segment Table Base Address High 2 (ERSTBA_HI2)—

Offset 2054h” on page 2220

00000000h

2058–205Bh

4

“Event Ring Dequeue Pointer Low 2 (ERDP_LO2)—Offset 2058h” on

00000000h

205C–205Fh

4

“Event Ring Dequeue Pointer High 2 (ERDP_HI2)—Offset 205Ch” on

00000000h

2060–2063h

4

“Interrupter 3 Management (IMAN3)—Offset 2060h” on page 2222

00000000h

2064–2067h

4

“Interrupter 3 Moderation (IMOD3)—Offset 2064h” on page 2222

00000FA0h

Table 211.

Summary of USB xHCI Memory Mapped I/O Registers—MBAR (Continued)

Offset

Size

(Bytes)

Register Name (Register Symbol)

Default Value