Intel E3815 FH8065301567411 Data Sheet

Intel

Product codes

FH8065301567411

Intel

®

Atom™ Processor E3800 Product Family

Datasheet

2167

3050–3053h

4

“Door Bell 21 (DOORBELL21)—Offset 3050h” on page 2260

00000000h

3054–3057h

4

“Door Bell 22 (DOORBELL22)—Offset 3054h” on page 2260

00000000h

3058–305Bh

4

“Door Bell 23 (DOORBELL23)—Offset 3058h” on page 2261

00000000h

305C–305Fh

4

“Door Bell 24 (DOORBELL24)—Offset 305Ch” on page 2262

00000000h

3060–3063h

4

“Door Bell 25 (DOORBELL25)—Offset 3060h” on page 2262

00000000h

3064–3067h

4

“Door Bell 26 (DOORBELL26)—Offset 3064h” on page 2263

00000000h

3068–306Bh

4

“Door Bell 27 (DOORBELL27)—Offset 3068h” on page 2263

00000000h

306C–306Fh

4

“Door Bell 28 (DOORBELL28)—Offset 306Ch” on page 2264

00000000h

3070–3073h

4

“Door Bell 29 (DOORBELL29)—Offset 3070h” on page 2264

00000000h

3074–3077h

4

“Door Bell 30 (DOORBELL30)—Offset 3074h” on page 2265

00000000h

3078–307Bh

4

“Door Bell 31 (DOORBELL31)—Offset 3078h” on page 2266

00000000h

307C–307Fh

4

“Door Bell 32 (DOORBELL32)—Offset 307Ch” on page 2266

00000000h

8000–8003h

4

“XECP_SUPP_USB2_0—Offset 8000h” on page 2267

02000802h

8004–8007h

4

“XECP_SUPP_USB2_1—Offset 8004h” on page 2267

20425355h

8008–800Bh

4

“XECP_SUPP_USB2_2—Offset 8008h” on page 2268

30190601h

8010–8013h

4

“XECP_SUPP_USB2_3 (Full Speed) (XECP_SUPP_USB2_3)—Offset

8010h” on page 2269

000C0021h

8014–8017h

4

“XECP_SUPP_USB2_4 (Low Speed) (XECP_SUPP_USB2_4)—Offset

8014h” on page 2270

05DC0012h

8018–801Bh

4

“XECP_SUPP_USB2_5 (High Speed) (XECP_SUPP_USB2_5)—Offset

8018h” on page 2270

01E00023h

8020–8023h

4

“XECP_SUPP_USB3_0—Offset 8020h” on page 2271

03000802h

8024–8027h

4

“XECP_SUPP_USB3_1—Offset 8024h” on page 2272

20425355h

8028–802Bh

4

“XECP_SUPP_USB3_2—Offset 8028h” on page 2272

10000107h

8030–8033h

4

“XECP_SUPP_USB3_3—Offset 8030h” on page 2273

00050134h

8040–8043h

4

“XECP_CMDM_STS0—Offset 8040h” on page 2274

00000CC1h

8044–8047h

4

“XECP_CMDM_STS1—Offset 8044h” on page 2276

03FC0000h

8048–804Bh

4

“XECP_CMDM_STS2—Offset 8048h” on page 2276

00000000h

804C–804Fh

4

“XECP_CMDM_STS3—Offset 804Ch” on page 2277

00000000h

8050–8053h

4

“XECP_CMDM_STS4—Offset 8050h” on page 2277

00000000h

8054–8057h

4

“XECP_CMDM_STS5—Offset 8054h” on page 2278

00000000h

8070–8073h

4

“Host Controller Capability (HOST_CTRL_CAP_REG)—Offset 8070h” on

0000FCC0h

8078–807Bh

4

“Override EP Flow Control (HOST_CLR_MASK_REG)—Offset 8078h” on

00000000h

807C–807Fh

4

“Clear Active IN EP ID Control (HOST_CLR_IN_EP_VALID_REG)—

Offset 807Ch” on page 2280

00000000h

8080–8083h

4

“Clear Poll Mask Control (HOST_CLR_PMASK_REG)—Offset 8080h” on

00000000h

8094–8097h

4

“Host Control Scheduler (HOST_CTRL_SCH_REG)—Offset 8094h” on

00008100h

Table 211.

Summary of USB xHCI Memory Mapped I/O Registers—MBAR (Continued)

Offset

Size

(Bytes)

Register Name (Register Symbol)

Default Value