Intel E3815 FH8065301567411 Data Sheet

Intel

Product codes

FH8065301567411

Intel

®

Atom™ Processor E3800 Product Family

2168

Datasheet

80A0–80A3h

4

“Global Port Control (HOST_CTRL_PORT_CTRL)—Offset 80A0h” on

00003C0Fh

80C0–80C3h

4

“AUX Reset Control (AUX_CTRL_REG)—Offset 80C0h” on page 2283

015FC0F0h

80C4–80C7h

4

“Super Speed Bandwidth Overload (HOST_BW_OV_SS_REG)—Offset

80C4h” on page 2286

004A4008h

80C8–80CBh

4

“High Speed TT Bandwidth Overload (HOST_BW_OV_HS_REG)—Offset

80C8h” on page 2287

0001A01Fh

80CC–80CFh

4

“Bandwidth Overload Full Low Speed (HOST_BW_OV_FS_LS_REG)—

Offset 80CCh” on page 2288

00014080h

80D0–80D3h

4

“System Bandwidth Overload (HOST_BW_OV_SYS_REG)—Offset

80D0h” on page 2288

00032010h

80D4–80D7h

4

“Scheduler Async Delay (HOST_CTRL_SCH_ASYNC_DELAY_REG)—

Offset 80D4h” on page 2289

00000000h

80D8–80DBh

4

“AUX Power PHY Reset (UPORTS_PON_RST_REG)—Offset 80D8h” on

00000000h

80E0–80E3h

4

“AUX Power Management Control (AUX_CTRL_REG1)—Offset 80E0h”

808DBCA0h

80E4–80E7h

4

“Battery Charge (BATTERY_CHARGE_REG)—Offset 80E4h” on

00000000h

80E8–80EBh

4

“Port Watermark (HOST_CTRL_WATERMARK_REG)—Offset 80E8h” on

00800080h

80EC–80EFh

4

“SuperSpeed Port Link Control (HOST_CTRL_PORT_LINK_REG)—Offset

80ECh” on page 2295

18010600h

80F0–80F3h

4

“USB2 Port Link Control 1 (USB2_LINK_MGR_CTRL_REG1)—Offset

80F0h” on page 2297

310003A0h

80F4–80F7h

4

“USB2 Port Link Control 2 (USB2_LINK_MGR_CTRL_REG2)—Offset

80F4h” on page 2300

80C40620h

80F8–80FBh

4

“USB2 Port Link Control 3 (USB2_LINK_MGR_CTRL_REG3)—Offset

80F8h” on page 2301

F865EB6Bh

80FC–80FFh

4

“USB2 Port Link Control 4 (USB2_LINK_MGR_CTRL_REG4)—Offset

80FCh” on page 2301

00008003h

8100–8103h

4

“Bandwidth Calc Control (HOST_CTRL_BW_CTRL_REG)—Offset 8100h”

00008008h

8108–810Bh

4

“Host Interface Control (HOST_IF_CTRL_REG)—Offset 8108h” on

00000001h

810C–810Fh

4

“Bandwidth Overload Burst (HOST_BW_OV_BURST_REG)—Offset

810Ch” on page 2303

00008020h

8128–812Fh

8

“USB Max Bandwidth Control 4 (HOST_CTRL_BW_MAX_REG)—Offset

8128h” on page 2304

0F42528505647F42h

8130–8133h

4

“USB2 Linestate Debug (LINESTATE_DEBUG_REG)—Offset 8130h” on

00000000h

8134–813Bh

8

“USB2 Protocol Gap Timer (USB2_PROTOCOL_GAP_TIMER_REG)—

Offset 8134h” on page 2306

000C3C640C05140Ch

813C–813Fh

4

“USB2 Protocol Bus Timeout Timer

(USB2_PROTOCOL_BTO_TIMER_REG)—Offset 813Ch” on page 2307

8D4258B8h

8140–8143h

4

“Power Scheduler Control-0 (PWR_SCHED_CTRL0)—Offset 8140h” on

0A019132h

8144–8147h

4

“Power Scheduler Control-2 (PWR_SCHED_CTRL2)—Offset 8144h” on

0000033Fh

Table 211.

Summary of USB xHCI Memory Mapped I/O Registers—MBAR (Continued)

Offset

Size

(Bytes)

Register Name (Register Symbol)

Default Value