Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
2173
18.7.5
Structural Parameters 3 (HCSPARAMS3)—Offset Ch
This register defines link exit latency related structural parameters. This register is 
modified and maintained by BIOS.
Access Method
Default: 00040001h
25:8
00000h
RW/L
Rsvd1: 
Reserved.
Power Well: 
Core
7:4
5h
RW/L
Event Ring Segment Table Max (ERSTMax): 
Valid values are 0-15. This field 
determines the maximum value supported by the Event Ring Segment Table Base Size 
registers (5.5.2.3.1), where 
     The maximum number of Event Ring Segment Table entries = 2^(ERST Max)  
 
e.g. if the ERST Max = 7, then the xHC Event Ring Segment Table(s) supports up to 128 
entries, if ERST Max = 15, then 32K entries, etc.
Power Well: 
Core
3:0
4h
RW/L
Isochronous Scheduling Threshold (IST): 
The value in this field indicates to system 
software the minimum distance (in time) that it is required to stay ahead of the host 
controller while adding TRBs, in order to have the host controller process them at the 
correct time. The value shall be specified in terms of number of frames/microframes.  
If bit [3] of IST is cleared to '0', software can add a TRB no later than IST[2.0] 
microframes before that TRB is scheduled to be executed.  
If bit [3] of IST is set to '1', software can add a TRB no later than IST[2:0] frames 
before that TRB is scheduled to be executed.  
Refer to the xHCI for USB specification for details on how software uses this information 
for scheduling isochronous transfers.
Power Well: 
Core
Bit 
Range
Default & 
Access
Field Name (ID): Description
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
Offset: 
MBAR Type: 
PCI Configuration Register (Size: 64 bits)
MBAR Reference: 
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
U2DEL
Rsvd1
U1DEL
Bit 
Range
Default & 
Access
Field Name (ID): Description
31:16
0004h
RW/L
U2 Device Exit Latency (U2DEL): 
Worst case latency to transition from U2 to U0. 
Applies to all root hub ports. The following are permissible values: 
0000h = Zero 
0001h = Less than 1 s 
0002h = Less than 2 s 
07FFh = Less than 2047 s. 
0800-FFFFh = Reserved 
Power Well: 
Core