Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
2176
Datasheet
18.7.7
Doorbell Offset (DBOFF)—Offset 14h
This register defines the offset of the Doorbell Array base address from the Base.
Access Method
Default: 00003000h
18.7.8
Runtime Register Space Offset (RTSOFF)—Offset 18h
This register defines the offset of the HCI Runtime Registers from the Base.
Access Method
Default: 00002000h
0
1b
RW/L
64-bit Addressing Capability (AC64): 
This flag documents the addressing range 
capability of this implementation. The value of this flag determines whether the xHC has 
implemented the high order 32 bits of 64 bit register and data structure pointer fields. 
Values for this flag have the following interpretation: 
0 = 32-bit address memory pointers implemented 
1 = 64-bit address memory pointers implemented 
If 32-bit address memory pointers are implemented, the xHC shall ignore the high order 
32 bits of 64 bit data structure pointer fields, and system software shall ignore the high 
order 32 bits of 64 bit xHC registers.
Power Well: 
Core
Bit 
Range
Default & 
Access
Field Name (ID): Description
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
Offset: 
MBAR Type: 
PCI Configuration Register (Size: 64 bits)
MBAR Reference: 
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
DBA
O
Rs
vd1
Bit 
Range
Default & 
Access
Field Name (ID): Description
31:2
00000C00h
RO
Doorbell Array Offset (DBAO): 
This field defines the offset in Dwords of the Doorbell 
Array base address from the Base i.e. the base address of the xHCI Capability register 
address space.
Power Well: 
Core
1:0
0h
RO
Rsvd1: 
Reserved.
Power Well: 
Core
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
Offset: 
MBAR Type: 
PCI Configuration Register (Size: 64 bits)
MBAR Reference: 
[B:0, D:20, F:0] + 10h