Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2177
18.7.9
USB Command (USBCMD)—Offset 80h
The Command Register indicates the command to be executed by the serial bus host
controller. Writing to the register causes a command to be executed.
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
RT
R
S
O
Rsvd
1
Bit
Range
Default &
Access
Field Name (ID): Description
31:5
0000100h
RO
Runtime Register Space Offset (RTRSO):
This field defines the 32-byte offset of the
xHCI Runtime Registers from the Base, i.e. Runtime Register Base Address = Base +
Runtime Register Set Offset.
Power Well:
Core
4:0
00h
RO
Rsvd1:
Reserved.
Power Well:
Core
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rsvd
2
EU
3
S
EW
E
CR
S
CSS
LHCRST
Rsvd
1
HS
E
E
INTE
HC
RST
RS
Bit
Range
Default &
Access
Field Name (ID): Description
31:12
00000h
RO
Rsvd2:
Reserved.
Power Well:
Core
11
0b
RW
Enable U3 MFINDEX Stop (EU3S):
When set to 1, the xHC may stop the MFINDEX
counting action if all Root Hub ports are in the U3, Disconnected, Disabled, or Powered-
off state. When cleared to 0 the xHC may stop the MFINDEX counting action if all Root
Hub ports are in the Disconnected, Disabled, Training, or Powered-off state. Refer to the
xHCI for USB specification for more information.
Power Well:
Core
10
0b
RW
Enable Wrap Event (EWE):
When set to 1, the xHC shall generate an MFINDEX Wrap
Event every time the MFINDEX register transitions from 03FFFh to 0. When cleared to 0
no MFINDEX Wrap Events are generated. Refer to the xHCI for USB specification for
more information.
When this register is exposed by a Virtual Function (VF), the generation of MFINDEX
Wrap Events to VFs shall be emulated by the VMM.
Power Well:
Core