Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2180
Datasheet
Default: 00000001h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Rs
vd3
HC
E
CN
R
SR
E
RS
S
SS
S
Rs
vd2
PC
D
EINT
HS
E
Rs
vd1
HCH
Bit
Range
Default &
Access
Field Name (ID): Description
31:13
00000h
RO
Rsvd3:
Reserved.
Power Well:
Core
12
0b
RO
Host Controller Error (HCE):
This bit is not preset in HC, this is deviation from XHCI
1.0 spec.
Power Well:
Core
11
0b
RO
Controller Not Ready (CNR):
This is deviation from XHCI 1.0 spec.
Power Well:
Core
10
0b
RW/C
Save/Restore Error (SRE):
If an error occurs during a Save or Restore operation, this
bit shall be set to 1. This bit shall be cleared to 0 when a Save or Restore operation is
initiated or when written with 1. Refer to the xHCI for USB specification for more
information. When this register is exposed by a Virtual Function (VF), the VMM
determines the state of this bit as a function of the Save/Restore completion status for
the selected VF. Refer to the xHCI for USB specification for more information.
Power Well:
Core
9
0b
RO
Restore State Status (RSS):
When the Controller Restore State (CRS) flag in the
USBCMD register is written with 1 this bit shall be set to 1 and remain 1 while the xHC
restores its internal state. When the Restore State operation is complete, this bit shall
be cleared to 0. Refer to the xHCI for USB specification for more information.
When this register is exposed by a Virtual Function (VF), the VMM determines the state
of this bit as a function of the restoring the state for the selected VF. Refer to the xHCI
for USB specification for more information.
Power Well:
Core
8
0b
RO
Save State Status (SSS):
When the Controller Save State (CSS) flag in the USBCMD
register is written with 1, this bit shall be set to 1 and remain 1 while the xHC saves its
internal state. When the Save State operation is complete, this bit shall be cleared to 0.
Refer to the xHCI for USB specification for more information. When this register is
exposed by a Virtual Function (VF), the VMM determines the state of this bit as a
function of the saving the state for the selected VF. Refer to the xHCI for USB
specification for more information.
Power Well:
Core
7:5
0h
RO
Rsvd2:
Reserved.
Power Well:
Core