Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2183

The Command Ring Control Register provides Command Ring control and status 

capabilities, and identifies the address and Cycle bit state of the Command Ring 

Dequeue Pointer.

Default: 00000000h

15:0

0000h

RW

When a Notification Enable bit is set, a Device 

Notification Event shall be generated when a Device Notification Transaction Packet is 

received with the matching value in the Notification Type field. For example, setting N1 

to '1' enables Device Notification Event generation if a Device Notification TP is received 

with a Notification Type field set to '1' (FUNCTIONAL_WAKE), etc.

Core

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 64 bits)

[B:0, D:20, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CRP

Rs

vd1

CRR

CA

CS

RCS

31:6

0000000h

RW

This field defines low order bits of the initial value of 

the 64-bit Command Ring Dequeue Pointer.  

Writes to this field are ignored when Command Ring Running (CCR) = '1'.  

If the CRCR is written while the Command Ring is stopped (CCR = '0'), the value of this 

field shall be used to fetch the first Command TRB the next time the Host Controller 

 register is written with the DB Reason field set to Host Controller Command.  

If the CRCR is not written while the Command Ring is stopped (CRR = '0') then the 

Command Ring shall begin fetching Command TRBs at the current value of the internal 

xHC Command Ring Dequeue Pointer.  

Reading this field always returns '0'.

Core

5:4

0h

RO

Reserved.

Core

3

0b

RO

This flag is set to '1' if the Run/Stop (R/S) bit is '1' 

and the Host Controller Doorbell register is written with the DB Reason field set to Host 

. It is cleared to '0' when the Command Ring is 'stopped' after 

writing a '1' to the Command Stop (CS) or Command Abort )CA) flags, or if the R/S bit 

is cleared to '0'

Core