Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2185

The Device Context Base Address Array Pointer Register identifies the base address of 

the Device Context Base Address Array. The memory structure referenced by this 

physical memory pointer is assumed to be physically contiguous and 64-byte aligned.

Default: 00000000h

The Device Context Base Address Array Pointer Register identifies the base address of 

the Device Context Base Address Array. The memory structure referenced by this 

physical memory pointer is assumed to be physically contiguous and 64-byte aligned.

31:0

00000000h

RW

This field defines high order bits of the initial value of 

the 64-bit Command Ring Dequeue Pointer.  

Writes to this field are ignored when Command Ring Running (CCR) = '1'.  

If the CRCR is written while the Command Ring is stopped (CCR = '0'), the value of this 

field shall be used to fetch the first Command TRB the next time the Host Controller 

 register is written with the DB Reason field set to Host Controller Command.  

If the CRCR is not written while the Command Ring is stopped (CRR = '0') then the 

Command Ring shall begin fetching Command TRBs at the current value of the internal 

xHC Command Ring Dequeue Pointer.  

Reading this field always returns '0'.

Core

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 64 bits)

[B:0, D:20, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DC

BA

AP

Rsvd

1

31:6

0000000h

RW

This field defines low order 

bits of the 64-bit base address of the Device Context Pointer Array, which is a table of 

address pointers that reference Device Context structures for the devices attached to 

the host.

Core

5:0

00h

RO

Reserved.

Core