Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2190

Datasheet

There are 9 PORTHLPM registers at offsets 48Ch, 49Ch, 4ACh, 4BCh, 4CCh, 4DCh, 

4ECh, 4FCh and 50Ch. This register is reset only by platform hardware during cold 

reset or in response to a Host Controller Reset (HCRST). The field definitions depend on 

the protocol supported. For USB3, this register is reserved and shall be treated by 

software as RsvdP. For USB2, the definition is given below. Fields contain parameters 

neccessary for xHC to automatically generate an LPM Token to the downstream device.

Default: 00000000h

2:0

0h

RW

Note: This register is sticky. This field is used by software to 

determine whether an L1- based suspend request (LPM transaction) was successful, 

specifically: 
•

0 = Invalid - This field shall be ignored by software. 

•

1 = Success - Port successfully transitioned to L1 (ACK) 

•

2 = Not Yet - Device is unable to enter L1 at this time (NYET) 

•

3 = Not Supported - Device does not support L1 transitions (STALL) 

•

4 = Timeout/Error - Device failed to respond to the LPM Transaction or an error 

occurred 

•

5-7  =  Reserved 

The value of this field is only valid when the port resides in the L0 or L1 state (PLS = 0 

or 2). Refer to the xHCI for USB specification for more information.

SUS

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 64 bits)

[B:0, D:20, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R

SVD

HIRD

D

L1T

O

HI

RD

M

31:14

00000h

RO

Reserved.

Core

13:10

0h

RW

System software sets this field to 

indicate to the recipient device how long the xHC will drive resume upon exit from L1. 

The HIRDD value is is encoded as follows: 
•

0h = 50 us (default) 

•

1h = 125 us 

•

2h = 200 us 

•

... 

•

Fh = 1.175ms 

The value of 0h is interpreted as 50 us. Each incrementing value adds 75 us to the 

previous value.

SUS