Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2197
18.7.26
Port X Hardware LPM Control Register (PORTHLPM3)—Offset
4ACh
There are 9 PORTHLPM registers at offsets 48Ch, 49Ch, 4ACh, 4BCh, 4CCh, 4DCh,
4ECh, 4FCh and 50Ch. This register is reset only by platform hardware during cold
reset or in response to a Host Controller Reset (HCRST). The field definitions depend on
the protocol supported. For USB3, this register is reserved and shall be treated by
software as RsvdP. For USB2, the definition is given below. Fields contain parameters
neccessary for xHC to automatically generate an LPM Token to the downstream device.
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PT
C
Rsvd
1
HL
E
L1DS
HI
RD
RWE
L1S
Bit
Range
Default &
Access
Field Name (ID): Description
31:28
0h
RW
Port Test Control (PTC):
Note: This register is sticky.
Power Well:
SUS
27:17
000h
RO
Rsvd1:
Reserved.
Power Well:
Core
16
0b
RO
Hardware LPM Enable (HLE):
Reserved.
Power Well:
SUS
15:8
00h
RW
L1 Device Slot (L1DS):
Note: This register is sticky.
Power Well:
SUS
7:4
0h
RW
Host Initiated Resume Duration (HIRD):
Note: This register is sticky.
Power Well:
SUS
3
0b
RW
Remote Wake Enable (RWE):
Note: This register is sticky.
Power Well:
SUS
2:0
0h
RW
L1 Status (L1S):
Note: This register is sticky.
Power Well:
SUS
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RS
VD
HIRD
D
L1T
O
HI
RDM