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Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
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Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
2209
18.7.35
Port X Hardware LPM Control Register (PORTHLPM6)—Offset 
4DCh
There are 9 PORTHLPM registers at offsets 48Ch, 49Ch, 4ACh, 4BCh, 4CCh, 4DCh, 
4ECh, 4FCh and 50Ch. This register is reset only by platform hardware during cold 
reset or in response to a Host Controller Reset (HCRST). The field definitions depend on 
the protocol supported. For USB3, this register is reserved and shall be treated by 
software as RsvdP. For USB2, the definition is given below. Fields contain parameters 
neccessary for xHC to automatically generate an LPM Token to the downstream device.
Access Method
Default: 00000000h
18.7.36
Port 1 Status and Control USB3 (PORTSC1USB3)—Offset 4E0h
Access Method
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
Offset: 
MBAR Type: 
PCI Configuration Register (Size: 64 bits)
MBAR Reference: 
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSV
D
HIRD
D
L1T
O
HIRD
M
Bit 
Range
Default & 
Access
Field Name (ID): Description
31:14
00000h
RO
RESERVED (RSVD): 
Reserved.
Power Well: 
Core
13:10
0h
RW
Host Initiated Resume Duration-Deep (HIRDD): 
System software sets this field to 
indicate to the recipient device how long the xHC will drive resume upon exit from L1. 
The HIRDD value is is encoded as follows: 
•
0h = 50 us (default) 
•
1h = 125 us 
•
2h = 200 us 
•
... 
•
Fh = 1.175ms 
The value of 0h is interpreted as 50 us. Each incrementing value adds 75 us to the 
previous value.
Power Well: 
SUS
9:2
00h
RW
L1 Timeout (L1TO): 
Timeout value for L1 inactivity timer. This field shall be set to 00h 
by assertion of PR to '1'. Following are permissible values: 00h: 128 us (default) 01h: 
256 us. ... FFh: 65,280us Note: This register is sticky.
Power Well: 
SUS
1:0
0h
RW
Host Initiated Resume Duration Mode (HIRDM): 
Indicates which HIRD value 
should be used. The following are permissible values: 
•
0 = Initiate L1 using HIRD only time out (default) 
•
1 = Initiate HIRDDon timeout. If rejected by device, initiate L1 using HIRD 
•
2,3  =  Reserved 
Note: This register is sticky.
Power Well: 
SUS