Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2216
Datasheet
18.7.44
Event Ring Segment Table Base Address High 1
(ERSTBA_HI1)—Offset 2034h
The Event Ring Segment Table Base Address Register identifies the start address of the
Event Ring Segment Table. There are 8 ERSTBA_HIx registers, with x = 1, 2, ... 8.
Access Method
Default: 00000000h
18.7.45
Event Ring Dequeue Pointer Low 1 (ERDP_LO1)—Offset 2038h
There are 8 ERDP_LOx registers, with x = 1, 2, ... 8.
Access Method
Bit
Range
Default &
Access
Field Name (ID): Description
31:6
0000000h
RW
Event Ring Segment Table Base Address Register (ERSTBA_LO):
This field
defines the low order bits of the start address of the Event Ring Segment Table.
Writing this register sets the Event Ring State Machine:EREP Advancement to the Start
state.
Refer to the xHCI for USB specification for more information.
This field shall not be modified if HCHalted (HCH) = 0.
Power Well:
Core
5:0
00h
RO
Rsvd1:
Reserved.
Power Well:
Core
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ERST
BA_HI
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
00000000h
RW
Event Ring Segment Table Base Address (ERSTBA_HI):
This field defines the high
order bits of the start address of the Event Ring Segment Table.
Writing this register sets the Event Ring State Machine:EREP Advancement to the Start
state.
Refer to the xHCI for USB specification for more information.
This field shall not be modified if HCHalted (HCH) = 0.
Power Well:
Core
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h