Intel E3815 FH8065301567411 Data Sheet

Product codes

FH8065301567411

Intel

Atom™ Processor E3800 Product Family

2228

Datasheet

Default: 00000000h

18.7.64

Event Ring Segment Table Base Address Low 4 (ERSTBA_LO4)—

Offset 2090h

The Event Ring Segment Table Base Address Register identifies the start address of the

Event Ring Segment Table. There are 8 ERSTBA_LOx registers, with x = 1, 2, ... 8.

Access Method

Default: 00000000h

Type:

Memory Mapped I/O Register

(Size: 32 bits)

Offset:

[MBAR] + 2088h

MBAR Type:

PCI Configuration Register (Size: 64 bits)

MBAR Reference:

[B:0, D:20, F:0] + 10h

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

vd1

Bit

Range

Default &

Access

Field Name (ID): Description

31:16

0000h

Rsvd1:

Reserved.

Power Well:

Core

15:0

0000h

Event Ring Segment Table Size (ERSTS):

This field identifies the number of valid

Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the

Event Ring Segment Table Base Address register. The maximum value supported by an

xHC implementation for this register is defined by the ERST Max field in the

HCSPARAMS2 register (see specification xHCI for USB).

For Secondary Interrupters: Writing a value of 0 to this field disables the Event Ring.

Any events targeted at this Event Ring when it is disabled shall result in undefined

behavior of the Event Ring.

For the Primary Interrupter: Writing a value of 0 to this field shall result in undefined

behavior of the Event Ring. The Primary Event Ring cannot be disabled.