Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
2232
Datasheet
18.7.70
Event Ring Segment Table Size 5 (ERSTSZ5)—Offset 20A8h
The Event Ring Segment Table Size Register defines the number of segments 
supported by the Event Ring Segment Table. There are 8 ERSTSZ registers. x = 1, 2, ... 
8.
Access Method
Default: 00000000h
18.7.71
Event Ring Segment Table Base Address Low 5 (ERSTBA_LO5)—
Offset 20B0h
The Event Ring Segment Table Base Address Register identifies the start address of the 
Event Ring Segment Table. There are 8 ERSTBA_LOx registers, with x = 1, 2, ... 8.
Access Method
15:0
0FA0h
RW
Interrupt Moderation Interval (IMODI): 
Default = '4000' (~1 ms). Minimum inter-
interrupt interval. The interval is specified in 250ns increments. A value of '0' disables 
interrupt throttling logic, and interrupts shall be generated immediately if IP = '0', EHB 
= '0', and the Event Ring is not empty.
Power Well: 
Core
Bit 
Range
Default & 
Access
Field Name (ID): Description
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
Offset: 
MBAR Type: 
PCI Configuration Register (Size: 64 bits)
MBAR Reference: 
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rsvd
1
ERST
S
Bit 
Range
Default & 
Access
Field Name (ID): Description
31:16
0000h
RO
Rsvd1: 
Reserved.
Power Well: 
Core
15:0
0000h
RW
Event Ring Segment Table Size (ERSTS): 
This field identifies the number of valid 
Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the 
Event Ring Segment Table Base Address register. The maximum value supported by an 
xHC implementation for this register is defined by the ERST Max field in the 
HCSPARAMS2 register (see specification xHCI for USB).  
For Secondary Interrupters: Writing a value of 0 to this field disables the Event Ring. 
Any events targeted at this Event Ring when it is disabled shall result in undefined 
behavior of the Event Ring.   
For the Primary Interrupter: Writing a value of 0 to this field shall result in undefined 
behavior of the Event Ring. The Primary Event Ring cannot be disabled.
Power Well: 
Core