Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2237

The Event Ring Segment Table Base Address Register identifies the start address of the 

Event Ring Segment Table. There are 8 ERSTBA_LOx registers, with x = 1, 2, ... 8.

Default: 00000000h

The Event Ring Segment Table Base Address Register identifies the start address of the 

Event Ring Segment Table. There are 8 ERSTBA_HIx registers, with x = 1, 2, ... 8.

15:0

0000h

RW

This field identifies the number of valid 

Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the 

Event Ring Segment Table Base Address register. The maximum value supported by an 

xHC implementation for this register is defined by the ERST Max field in the 

HCSPARAMS2 register (see xHCI for USB specification).  

For Secondary Interrupters: Writing a value of 0 to this field disables the Event Ring. 

Any events targeted at this Event Ring when it is disabled shall result in undefined 

behavior of the Event Ring.   

For the Primary Interrupter: Writing a value of 0 to this field shall result in undefined 

behavior of the Event Ring. The Primary Event Ring cannot be disabled.

Core

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 64 bits)

[B:0, D:20, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ERS

T

BA_L

O

Rs

vd1

31:6

0000000h

RW

This field 

defines the low order bits of the start address of the Event Ring Segment Table.  

Writing this register sets the Event Ring State Machine:EREP Advancement to the Start 

state.  

Refer to the xHCI for USB specification for more information.  

This field shall not be modified if HCHalted (HCH) = 0.

Core

5:0

00h

RO

Reserved.

Core