Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2238
Datasheet
Default: 00000000h
18.7.80
Event Ring Dequeue Pointer Low 6 (ERDP_LO6)—Offset 20D8h
There are 8 ERDP_LOx registers, with x = 1, 2, ... 8.
Access Method
Default: 00000000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ER
S
T
B
A
_
H
I
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
00000000h
RW
Event Ring Segment Table Base Address (ERSTBA_HI):
This field defines the high
order bits of the start address of the Event Ring Segment Table.
Writing this register sets the Event Ring State Machine:EREP Advancement to the Start
state.
Refer to the xHCI for USB specification for more information.
This field shall not be modified if HCHalted (HCH) = 0.
Power Well:
Core
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ER
D
P
EH
B
DES
I
Bit
Range
Default &
Access
Field Name (ID): Description
31:4
0000000h
RW
Event Ring Dequeue Pointer (ERDP):
This field defines the low order bits of the 64-
bit address of the current Event Ring Dequeue Pointer.
Power Well:
Core
3
0b
RW/C
Event Handler Busy (EHB):
This flag shall be set to 1 when the IP bit is set to 1 and
cleared to 0 by software when the Dequeue Pointer register is written. Refer to the xHCI
for USB specification for more information.
Power Well:
Core