Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
2243
Default: 00000000h
18.7.88
Event Ring Dequeue Pointer High 7 (ERDP_HI7)—Offset 20FCh
There are 8 ERDP_HIx registers, with x = 1, 2, ... 8.
Access Method
Default: 00000000h
18.7.89
Interrupter 8 Management (IMAN8)—Offset 2100h
The Interrupter Management registers allow system software to enable, disable, detect 
and force xHC interrupts. There are 8 IMAN registers. x = 1, 2, ... 8.
Access Method
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ER
DP
EH
B
DES
I
Bit 
Range
Default & 
Access
Field Name (ID): Description
31:4
0000000h
RW
Event Ring Dequeue Pointer (ERDP): 
This field defines the low order bits of the 64- 
bit address of the current Event Ring Dequeue Pointer.
Power Well: 
Core
3
0b
RW/C
Event Handler Busy (EHB): 
This flag shall be set to 1 when the IP bit is set to 1 and 
cleared to 0 by software when the Dequeue Pointer register is written. Refer to the xHCI 
for USB specification for more information.
Power Well: 
Core
2:0
0h
RW
Dequeue ERST Segment Index (DESI): 
This field may be used by the xHC to 
accelerate checking the Event Ring full condition. This field is written with the low order 
3 bits of the offset of the ERST entry which defines the Event Ring segment that the 
Event Ring Dequeue Pointer resides in.
Power Well: 
Core
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
Offset: 
MBAR Type: 
PCI Configuration Register (Size: 64 bits)
MBAR Reference: 
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ERDP
Bit 
Range
Default & 
Access
Field Name (ID): Description
31:0
00000000h
RW
Event Ring Dequeue Pointer (ERDP): 
This field defines the high order bits of the 64- 
bit address of the current Event Ring Dequeue Pointer.
Power Well: 
Core