Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2249
18.7.97
Door Bell 2 (DOORBELL2)—Offset 3004h
Door Bell registers are an array of 64 registers, with 0 to 32 being used by the XHC and
the rest being reserved. Refer to the xHCI for USB specification for more information.
Access Method
Default: 00000000h
7:0
00h
RW
DB Target (DBT):
This field defines the target of the doorbell reference. The table
below defines the xHC notification that is generated by ringing the doorbell. Note that
Doorbell Register 0 is dedicated to Command Ring and decodes this field differently than
the other Doorbell Registers.
•
•
Device Context Doorbells (1-255)
•
0 = Reserved
•
1 = Control EP 0 Enqueue Pointer Update
•
2 = EP 1 OUT Enqueue Pointer Update
•
3 = EP 1 IN Enqueue Pointer Update
•
4 = EP 2 OUT Enqueue Pointer Update
•
5 = EP 2 IN Enqueue Pointer Update
•
...
•
30 = EP 15 OUT Enqueue Pointer Update
•
31 = EP 15 IN Enqueue Pointer Update
•
32:247 = Reserved
•
248:255 = Vendor Defined
•
Host Controller Doorbell (0)
•
0 = Command Doorbell
•
248:255 = Vendor Defined
This field returns '0' when read, and should be treated as 'undefined' by software. When
the Command Doorbell is written, the DB Stream ID field shall be cleared to 0.
Power Well:
Core
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DBSID
Rsvd1
DB
T
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0000h
RW
DB Stream ID (DBSID):
Refer to field descriptions for the DOORBELL1 register.
Power Well:
Core
15:8
00h
RO
Rsvd1:
Reserved.
Power Well:
Core
7:0
00h
RW
DB Target (DBT):
Refer to field descriptions for the DOORBELL1 register.
Power Well:
Core