Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2281
18.7.148 Host Control Scheduler (HOST_CTRL_SCH_REG)—Offset 8094h
Access Method
Default: 00008100h
Bit
Range
Default &
Access
Field Name (ID): Description
31:10
000000h
RO
RESERVED (RSVD):
Reserved.
Power Well:
Core
9:5
00h
RW
Slot Number Default Config (SNDC):
5bits of slot number as a default configuration.
It can scale to max of 128 slots
Power Well:
Core
4:1
0h
RW
EP Number (EP_NUM):
4bits of EP number
Power Well:
Core
0
0b
RW
Clear Internal Scheduler's Poll Mask (CISPM):
This is a register that is used to
clear the internal scheduler's poll mask that is used to indicate whether we need to poll
this EP. This is used for USB2. Bit0 indicates the direction of the EP
Power Well:
Core
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
SC
HE
D_HO
ST_C
TRL_C
O
N
T
TT
E
_
H
O
S
T
_
C
T
R
L
CA
CH
E_S
Z
_CTRL
MAX_E
P
_SL
O
T
TO
_SCRA
TCH_P
AD_EN
SC
HE
D_HO
ST_C
TRL
Bit
Range
Default &
Access
Field Name (ID): Description
31:21
000h
RW
Scheduler Host Control Reg Cont (SCHED_HOST_CTRL_CONT):
method of USB2
port periodic done check (off by default)
Power Well:
Core
20:13
04h
RW
TTE Host Control (TTE_HOST_CTRL):
(0): disable interrupt complete split limit to 3
microframes (1): disable checking of missed microframes (2): disable split error request
w/NULL pointer on speculative INs with data payload and no TRB. (3): disable deferred
split error request on speculative IN with data payload and no TRB. (7:4): reserved
Power Well:
Core