Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2282
Datasheet
18.7.149 Global Port Control (HOST_CTRL_PORT_CTRL)—Offset 80A0h
Access Method
Default: 00003C0Fh
12:11
0h
RW
Cache Size Control Reg (CACHE_SZ_CTRL):
•
•
0 = 64
•
1 = 32
•
2,3 = 16
Power Well:
Core
10:9
0h
RW
Maximum EP Per Slot (MAX_EP_SLOT):
•
•
0 = 32
•
1 = 16
•
2 = 8
•
3 = 4
Power Well:
Core
8
1b
RW
Turn on scratch_pad_en (TO_SCRATCH_PAD_EN):
Reserved.
Power Well:
Core
7:0
00h
RW
Scheduler Host Control Reg (SCHED_HOST_CTRL):
•
•
(0): disable poll delay
•
(1): disable TRM active in EP valid check
•
(2): enable TTE overlap prevention on interrupt IN EPs (at cost of possible service
interval slip)
•
(3) enable TTE overlap prevention on interrupt OUT EPs (at cost of possible service
interval slip)
•
(5:4) scheduler sort pattern
•
-- 00 (default) search ISO ahead of interrupt within each service interval
•
-- 01 - search USB2-ISO, USB3-ISO, USB2-Interrupt, USB3-Interrupt within each
service interval
•
-- 10 - search strictly by interval
•
-- 11 - search all ISO intervals ahead interrupt intervals and within each interval,
USB2 ahead of USB3
•
(6): disable 1 pack scheduling limit when ISO pending in present microframe
•
(7): enable check to stop scheduling on port that are not connected
Power Well:
Core
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1
RSV
D
EN_
PP_RE
G_PDWN
RESE
RVE
D
EN_USB_PP2_EN
EN_U3P
_CG
EN_P
3_OVR_P2_RD
EN_UPP
_RST_EP3
RSV
D
_1