Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2285
22
1b
RW
RESERVED (RSVD_1):
Reserved.
Power Well:
SUS
21
0b
RW
Ignore HC Reset USB2 (IGN_HC_RST_U2):
When set to '1', ignore HC reset to reset
the USB2 Port logic.
Power Well:
SUS
20
1b
RW
Ignore HC Reset USB PHY (IGN_HC_RST_UP_POR):
When set to '1', ignore HC
reset to the USB PHY power-on reset.
Power Well:
SUS
19
1b
RW
Enable PCIe Link-Down Reset (EN_PLD_RST):
Enable a reset due to a PCIe link-
down condition. The PCIe link down condition will cause a HC reset liked. If this bit is set
1, the PCIe link down condition will only reset the PCIe core.
Power Well:
SUS
18
1b
RW
Enable EEPROM Reload On Power Up (EN_EEP_REL_PU):
When set to '1', enable
EEPROM reload on every main power-up.
Power Well:
SUS
17
1b
RW
Ignore HC Reset PCIe PHY PIPE (IGN_HC_RST_PPP):
When set to '1', ignore HC
reset to the PCIe PHY PIPE reset.
Power Well:
SUS
16
1b
RW
Ignore LTSSM Reset USB PHY PIPE (IGN_LRST_UPP):
When set to '1', ignore the
LTSSM of USB link state transition caused reset to USB PHY PIPE reset.
Power Well:
SUS
15
1b
RW
Ignore Warm Reset USB PHY Power (IGN_WR_UPP):
When set to '1', ignore
warm reset the USB PHY power on reset.
Power Well:
SUS
14
1b
RW
Allow Core PCIe Link Down Reset (ALL_CPLD_RST):
When set to '1', allow PCIe
link down to cause a reset to the rest of the core.
Power Well:
SUS
13
0b
RW
Ignore Hot Reset USB3 (IGN_HR_U3):
When set to '1', ignore hot reset to the USB3
port logic.
Power Well:
SUS
12
0b
RW
Ignore Warm Reset USB3 (IGN_WR_U3):
When set to '1', ignore warm reset to the
USB3 port logic
Power Well:
SUS
11
0b
RW
Ignore Main Power Up Reset USB3 (IGN_MPU_RST_U3):
When set to '1', ignore
main power up reset to USB3 port logic.
Power Well:
SUS
10
0b
RW
Ignore Main Power Up Reset USB2 (IGN_MPU_RST_U2):
When set to '1', ignore
main power up reset to USB2 port logic.
Power Well:
SUS
Bit
Range
Default &
Access
Field Name (ID): Description