Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2286
Datasheet
18.7.151 Super Speed Bandwidth Overload (HOST_BW_OV_SS_REG)—
Offset 80C4h
Access Method
Default: 004A4008h
9
0b
RW
Ignore Main Power Up Reset PCIe Core (IGN_MPU_RST_PC):
When set to '1',
ignore main power up reset to PCIe core.
Power Well:
SUS
8
0b
RW
Ignore Main Power Up Reset PCIe PHY (IGN_MPU_RST_PP):
When set to '1',
ignore main power up reset to PCIe PHY.
Power Well:
SUS
7
1b
RW
Ignore HC Reset USB PHY (IGN_HC_RST_UP):
When set to '1', ignore HC reset to
the USB PHY.
Power Well:
SUS
6
1b
RW
Ignore Warm Reset USB PHY (IGN_WRST_UP):
When set to '1', ignore warm reset
to the USB PHY.
Power Well:
SUS
5
1b
RW
Enable HC Reset Per Port Isolation (EN_HC_RST_PPI):
Enables the HC reset or
per port reset isolation function.
Power Well:
Core
4
1b
RW
Allow Power Off Power Domain Reset (ALL_PO_PDRST):
When set to '1', allow
main power off condition to trigger a main power domain reset.
Power Well:
SUS
3
0b
RW
Ignore Wait For PERST# During Power Shut Down (IGN_PERST_PSD):
When set
to '1', ignore waiting for PERST# deassertion during main power shut down.
Power Well:
SUS
2
0b
RW
Ignore Fundamental Reset During AUX Power Up (IGN_FRST_AUX_PU):
If this
bit is set and a fundamental reset is asserted during AUX power up, then PERST# shall
be ignored and a timeout will be allowed to deassert fundamental reset instead.
Power Well:
SUS
1:0
0h
RW
Trigger Fundamental Reset (TRIG_FRST):
Writing to bit(1:0) to value of 2'b11 will
cause a fundamental reset
Power Well:
SUS
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h