Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2296
Datasheet
25
0b
RW
Direct Link To U0 (DL_U0):
•
•
0 = Normal operation mode
•
1 = Direct link to U0
This bit is for test purposes only. It shall be written 0 in normal operation mode.
Power Well:
Core
24:21
0h
RW
Forced Compliance Pattern (FORCED_CMP_PAT):
Compliance pattern to be forced
to enter compliance mode This value is for test purpose only.
Power Well:
Core
20
0b
RW
Enable Link Error Slave Count (EN_LES_CNT):
•
•
0 = Disable link error slave count
•
1 = Enable link error slave count
Power Well:
Core
19:17
0h
RW
Debug Mode Select (DEBUG_MD_SEL):
Reserved.
Power Well:
Core
16:15
2h
RW
PHY Low Power Latency (PHY_LP_LAT):
This field defines the latency to drive the
PHY to enter low power mode.
•
•
0 = 4 cycles
•
1 = 8 cycles
•
2 = 16 cycles
•
3 = 32 cycles
Power Well:
Core
14:12
0h
RW
Link Recovery Minimum Time (LR_MIN_TM):
This value defines the minimum time
for the link to stay in Recovery.Active other than from U3. The granuity is 128us.
Power Well:
Core
11:9
3h
RW
Link Polling Minimum Time (LP_MIN_TM):
This value defines the minimum time for
the link to stay in Polling.Active and Recovery.Active from U3. The granuity is 128us.
Power Well:
Core
8
0b
RW
Force Link Accept PM Command (FORCE_LA_PMC):
•
•
0 = Normal operation mode
•
1 = Force link to accept power management command
Power Well:
Core
7
0b
RW
Direct Link Recovery U0 (DL_REC_U0):
•
•
0 = Normal operation mode
•
1 = Direct link to Recovery from U0
Power Well:
Core
6
0b
RW
Link Fast Training Mode (LINK_FTM):
•
•
0 = Normal operation mode
•
1 = Link fast training mode
This bit should be written 0 in normal operation.
Power Well:
Core
Bit
Range
Default &
Access
Field Name (ID): Description