Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2297

This set of registers is used to control the USB set of timers. They are spread over 4 

registers each 32 bits wide.

Default: 310003A0h

5

0b

RW

Disable Link Scrambler (DIS_LINK_SCRAM): 
•

0 = Enable link scrambler 

•

1 = Disable link scramber 

Core

4

0b

RW

Direct Link U3 From U0 (DL_U3_U0): 
•

0 = Normal operation mode 

•

1 = Direct link to U3 from U0 

This bit is for test purposes only. It shall be written 0 in normal operation mode.

Core

3

0b

RW

Direct Link U3 From U0 (DL_U2_U0): 
•

0 = Normal operation mode 

•

1 = Direct link to U2 from U0 

This bit is for test purposes only. It shall be written 0 in normal operation mode.

Core

2

0b

RW

Direct Link U3 From U0 (DL_U1_U0): 
•

0 = Normal operation mode 

•

1 = Direct link to U1 from U0 

This bit is for test purposes only. It shall be written 0 in normal operation mode.

Core

1

0b

RW

Enable Link Loopback Master Mode (EN_LINK_LB_MAST): 
•

0 = Disable link loopback master mode 

•

1 = Enable link loopback master mode 

Core

0

0b

RW

Disable Link Compliance Mode (DIS_LINK_CM): 
•

0 = Enable link compliance mode 

•

1 = Disable link compliance mode 

Core

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 64 bits)

[B:0, D:20, F:0] + 10h