Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2308
Datasheet
18.7.172 Power Scheduler Control-0 (PWR_SCHED_CTRL0)—Offset
8140h
Access Method
Default: 0A019132h
18.7.173 Power Scheduler Control-2 (PWR_SCHED_CTRL2)—Offset
8144h
These bit enable by EP type those EPs classes that are considered for determining next
periodic active interval for pre-wake of the periodic_active signal. EP classes that are
disabled may never be observed in setting of the periodic_active signal.
20:10
096h
RW
Bus timeout count for FS (FS_BUS_TO):
Reserved.
Power Well:
Core
9:0
0b8h
RW
Bus timeout count for HS (HS_BUS_TO):
Reserved.
Power Well:
Core
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0
EIH
BPS
A
W
BPSMID
Bit
Range
Default &
Access
Field Name (ID): Description
31:24
0ah
RW
Engine Idle Hysteresis (EIH):
This register controls the min. idle span that has to be
observed from the engine idle indicators before the power state flags (xhc_*_idle) will
indicate a 1.
Power Well:
Core
23:12
019h
RW
Backbone PLL Shutdown Advance Wake (BPSAW):
This register controls the time
before the next scheduled transaction where the Backbone PLL request will assert.
•
•
Register Format:
•
Bits [11:7] # of 125us uframes
•
Bits [6:0] # of microseconds (0-124)
Power Well:
Core
11:0
132h
RW
Backbone PLL Shutdown Min. Idle Duration (BPSMID):
The sum of this register
plus the Backbone PLL Shutdown Advance Wake form to a Total Idle time. When the
next scheduled periodic transaction is after present time + Total Idle, the Backbone PLL
request will de-assert, allowing the PLL to shutdown. Register Format:
•
•
Bits [11:7] # of 125us uframes
•
Bits [6:0] # of microseconds (0-124)
Power Well:
Core