Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2310
Datasheet
18.7.174 Latency Tolerance Control 0 (HOST_IF_LAT_TOL_CTRL_REG0)—
Offset 8150h
The Latency Tolerance Control Register is used by SW to control which BELT is returned
when this register is read. SW shall write to this register to program a Slot-ID, Port-ID
and BELT Select to determine which BELT is selected. When this register is read the
selected BELT is returned.
Access Method
Default: 00000000h
0
1b
RW
SS ISO-IN Alarm (SS_ISO_IN_ALRM):
Reserved.
Power Well:
Core
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BE
LT
_
S
EL
Rsvd1
PO
R
T
_
S
E
L
Rs
vd
BE
LT
V
SL
O
T
_S
EL
Bit
Range
Default &
Access
Field Name (ID): Description
31:30
0h
WO
BELT Select (BELT_SEL):
This field determines what value will be selected to read
back from SW when reading this register.
•
•
0 = Returns the SW programmed Latency Tolerance Value
•
1 = Returns the Lowest BELT in the Host
•
2 = Returns the BELT for the requested Slot-ID (Slot Select)
•
3 = Returns the BELT for the requested Port-ID (Port Select)
Power Well:
Core
29:17
0h
RO
Rsvd1:
Reserved.
Power Well:
Core
16
0h
WO
Port Select (PORT_SEL):
Used to select the BELT for a given Port # when the BELT
Select is programmed to select the Port-ID (this field is 0 based)
Power Well:
Core
15:12
0h
RO
Rsvd:
Reserved.
Power Well:
Core
11:5
0h
RO
BELT Value (BELTV):
Value of selected BELT is return in this field
Power Well:
Core