Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2312
Datasheet
24
1b
RW
Enable L1 exit notification to SNPS PCIe core (EN_L1_EXIT_NOTIF_PCIE):
This
bit enables a L1 exit notification to SNPS PCIe core. There is a case where USB ports
have waked up and AUX PM module has started the wakeup process. The AUX PM
control state got into a wait for P0 state because it needs to wait until PCie core to signal
powerdown state change. Due to the fact that the core is in D3Hot, there is no run_stop
bit set such that no internal interrupt will be fired. This causes the LTSSM of PCIe stayed
in L1 even though AUX PM has known that it needs an L1 exit. This bit works together
with bit21 of this register.
•
•
1 = enables this feature
•
0 = disables this feature.
Power Well:
SUS
23
0b
RW
DISABLE PLC ON DISCONNECT (DIS_PLC_ON_DISCONNECT):
•
•
1 = do not assert PLC for disconnection
•
0 = assert PLC for disconnection
Power Well:
SUS
22
0b
RW
TREAT_IDLE_AS_TS2_IN_LTSSM_WAIT_4_TS2:
This bit enables a feature in PCie
core LTSSM to treat IDLE received as TS2 when LTSSM is in wait for TS2 receive state.
This is a function requested from PHY where it is possible to not able to receive TS2
without error.
•
•
1 = treat Logic IDLE as TS2 received when in some PCIe LTSSM state.
•
0 = disable this feature.
Power Well:
SUS
21
1b
RW
Disable p2 overwrite due to the D3HOT where PCIe core enters the L1
(DIS_P2_OVERWRITE_DUE2_D3HOT):
We added a feature where if PCIe core
LTSSM enters L1 due to the D3hot, the aux PM control will not start a P2 overwrite
function in anticipating for the next L23 enter.
•
•
1 = disables p2 overwrite due to the D3HOT where PCIe core enters the L1.
•
0 = enables P2 overwrite even if we are in D3Hot.
Power Well:
SUS
20
1b
RW
Enable the port to enter U3 automatically when in U1/U2
(ENABLE_AUTO_U3_ENTRY_FROM_U2_U3):
•
•
1 = enables the port to enter U3 automatically when in U1/U2
•
0 = disables the port to enter U3 automatically when in U1/U2
Power Well:
SUS
19
1b
RW
No linkdown reset is issued during low power state
(DIS_LINKDOWN_RST_DURING_LOW_POWER):
No linkdown reset is issued
during low power state.
Power Well:
SUS
18
0b
RW
EN_EXIT_DEEP_SLEEP_IF_PCIE_IN_P0:
This bit enables a feature in AUX PM
module where if PCIe core LTSSM is in P0 for a duration of time, we will exit the deep
sleep state. This is for failure control in case.
•
•
1 = enable this feature
•
0 = disable this feature
Power Well:
SUS
17
0b
RW
U2_EXIT_LFPS_TIMER_VALUE:
This bit selects U2 exit LFPS timer value.
•
0 = 320ns 400ns in 25MHz domain
•
1 = 240ns 320ns in 25MHz domain
Power Well:
SUS
Bit
Range
Default &
Access
Field Name (ID): Description