Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2313
16
1b
RW
EN_EXIT_DEEP_SLEEP_ON_USB_PORT_WAKEUP:
This bit enables a function that
AUX PM module exits from the deep sleep state due to the USB ports wakeup level
signal. We have added this feature where USB ports will generated a wakeup level signal
to wakeup the AUX PM module if it is in deep sleep state and this level signal will be
cleared if the change bits are updated by software.
•
•
1 = enables this function
•
0 = disables this function which means that a wakeup pulse generated from each
USB PortSC event will wake up the AUX PM module from deep sleep if the D3 state
is programmed.
Power Well:
SUS
15:14
0h
RW
P3_ENTRY_TIMEOUT:
This field defines the timeout value to enter P3 mode in U2.
•
00 = 7us 8us
•
01 = 511us 512us
•
10 = disables the timer (0us)
•
11 = disables the timer (0us)
Power Well:
SUS
13
0b
RW
Enable U2 P3 Mode (EN_U2_P3):
•
•
0 = Disable U2 P3 mode
•
1 = Enable U2 P3 mode
Power Well:
SUS
12:11
0h
RW
Fine Debug Mode Select (FINE_DM_SEL):
Reserved.
Power Well:
SUS
10
0b
RW
Enable Low Power State Based Core Clock Gating (EN_LP_CORE_CG):
When set
to '1', enable core clock gating based on low power state entered
Power Well:
SUS
9
1b
RW
Disable USB3 Port Status Changed Event (DIS_U3_PORT_SCE):
•
•
0 = Enable USB3 port status change event generation if any change bit is not
cleared
•
1 = Disable USB3 port status change event generation if any change bit is not
cleared Bit 12 default 0
Power Well:
SUS
8:4
00h
RW
Debug Mode Select Register (DEB_MODE_SEL):
Reserved.
Power Well:
SUS
3
0b
RW
Enable Auto Wakeup Non-IDLE (EN_AWAK_NIDLE):
When set to 1, enables the
auto wakeup function when engine has identified non IDLE condition.
Power Well:
SUS
2
1b
RW
Enable PM Control P1 Exit P2 (EN_PMC_P1_EXIT_P2):
When set to 1, enables the
PM control module to transition to P1 instead of P0 upon exit from P2.
Power Well:
SUS
1
1b
RW
Enable PCIe PIPE CLK Isolation (EN_PP_CLK_ISOL):
When set to 1, enables the
PCIe PIPE CLK to be isolated when main power is removed.
Power Well:
SUS
Bit
Range
Default &
Access
Field Name (ID): Description