Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2317
13:12
0h
RW
Rx Detect Timer when port Aux Clock is Gated (RX_DT_ACG):
This field defines
the value of the timer used to perform Rx Detect when port Aux Clock has been gated.
•
•
0x0 = 100ms
•
0x1 = 12ms
•
Others = Reserved
Note: This timer shall use the Fast Training Timer Tick (about 1us tick) for simulation
purposes. For Fast Training mode, the above timeouts will become about 11us and about
100us, +/- implementation uncertainty, respectively.
Power Well:
SUS
11:8
4h
RW
U2 Residency Before ModPHY Clock Gating (U2R_BM_CG):
Before gating ModPHY
Aux clock, Host Controller shall wait for this time in U2. This time is meant to ensure
that the attached device has entered U2 as well.
•
•
0x0 = 1us
•
0x1 = 128us
•
0x2 = 256us
•
0x3 = 512us
•
0x4 = 640us
•
0x5 = 768us
•
0x6 = 896us
•
0x7 = 1024us
•
Others = Reserved
Note: This counter shall start counting once pipe has entered PS3 state in response to
link in U2.
Power Well:
SUS
7
0h
RW
Frame Timer Clock Gating Ports in U2 Enable (FTCGPU2E):
This bit, when set,
allows Host Controller to gate the clock to the Frame Timer when ports are in U2.
Power Well:
SUS
6
0b
RW
USB2 port clock throttle enable (USB2_PC_TE):
When set, allows the Aux clock
into the USB2 ports to be throttled when conditions allow.
Power Well:
SUS
5
0b
RW
XHCI Engine Aux clock gating enable (XHCI_AC_GE):
When set, allows the aux
clock into the XHCI engine to be gated when idle. Usage of this bit is further qualified
with xHC Dynamic Clock Gating Disable fuse. If the fuse disables dynamic clock gating,
Aux clock gating will not be enabled either. This bit always returns the value that was
written to it irrespective of the setting of xHC Dynamic Clock Gating Disable fuse.
Power Well:
SUS
4
0b
RW
XHCI Aux PM block clock gating enable (XHCI_APMB_CGE):
When set, allows the
aux clock into the Aux PM block to be gated when idle. Usage of this bit is further
qualified with xHC Dynamic Clock Gating Disable fuse. If the fuse disables dynamic clock
gating, Aux clock gating will not be enabled either. This bit always returns the value that
was written to it irrespective of the setting of xHC Dynamic Clock Gating Disable fuse.
Power Well:
SUS
3
0b
RW
USB3 Aux Clock Trunk Gating Enable (USB3_AC_TGE):
When set, allows Aux Clock
Trunk feeding to USB3.0 ports to be gated when port Aux clock is gated at all USB3.0
ports and all USB3.0 modPHY instances. Usage of this bit is further qualified with xHC
Dynamic Clock Gating Disable fuse. If the fuse disables dynamic clock gating, Aux clock
gating will not be enabled either. This bit always returns the value that was written to it
irrespective of the setting of xHC Dynamic Clock Gating Disable fuse.
Power Well:
SUS
Bit
Range
Default &
Access
Field Name (ID): Description