Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
2318
Datasheet
18.7.179 USB LPM Parameters (USB_LPM_PARAM)—Offset 8170h
Access Method
Default: 00090032h
2
0b
RW
USB3 Port Aux/Port clock gating enable (USB3_AP_CGE): 
When set, allows the 
aux_pclk clock into the USB3 port to be gated when conditions are met. Usage of this bit 
is further qualified with xHC Dynamic Clock Gating Disable fuse. If the fuse disables 
dynamic clock gating, Aux clock gating will not be enabled either. This bit always returns 
the value that was written to it irrespective of the setting of xHC Dynamic Clock Gating 
Disable fuse.
Power Well: 
SUS
1
0b
RW
ModPHY port Aux clock gating enable in U2 (MPP_AC_GEU2): 
When set, allows 
the aux clock into the ModPhy to be gated when Link is in U2 and pipe has been in PS3 
for at least the time defined by U2 Residency Before ModPHY Clock Gating field. Usage 
of this bit is further qualified with xHC Dynamic Clock Gating Disable fuse. If the fuse 
disables dynamic clock gating, Aux clock gating will not be enabled either. This bit 
always returns the value that was written to it irrespective of the setting of xHC 
Dynamic Clock Gating Disable fuse.
Power Well: 
SUS
0
0b
RW
ModPHY port Aux clock gating enable in Disconnected, U3 or Disabled 
(MPP_AC_GE_DDU3): 
When set, allows the aux clock into the ModPHY to be gated 
when Link is in Disconnected, U3 or Disabled state. Usage of this bit is further qualified 
with xHC Dynamic Clock Gating Disable fuse. If the fuse disables dynamic clock gating, 
Aux clock gating will not be enabled either. This bit always returns the value that was 
written to it irrespective of the setting of xHC Dynamic Clock Gating Disable fuse.
Power Well: 
SUS
Bit 
Range
Default & 
Access
Field Name (ID): Description
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
Offset: 
MBAR Type: 
PCI Configuration Register (Size: 64 bits)
MBAR Reference: 
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0
RSVD
MI
N
_
U
3
E
_
LF
PS
_
D
M
IN_U2_ELFPS_D
X
H
CI_M
AX_PING
_
LFPS
RSVD
_1
X
H
CI_BESL
_
HIRD_D
T
Bit 
Range
Default & 
Access
Field Name (ID): Description
31:22
000h
RO
Reserved (RSVD): 
Reserved.
Power Well: 
Core