Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2319
18.7.180 xHC Latency Tolerance Parameters - LTV Control (XLTP_LTV1)—
Offset 8174h
Access Method
21:19
001b
RW
Min U3 Exit LFPS Duration (MIN_U3E_LFPS_D):
This field defines the minimum
duration of LFPS driven by Host Controller upon U3 exit LFPS handshake. Note that
there is an uncertainty of +-16us in actual duration driven by the Host Controller.
•
•
•
0b000 = 96us
•
0b001 = 160us
•
0b010 = 224us
•
0b011 = 288us
•
0b100 = 352us
•
0b101 = 416us
•
0b110 = 480us
•
0b111 = 544us
Power Well:
SUS
18:16
001b
RW
Min U2 Exit LFPS Duration (MIN_U2_ELFPS_D):
This field defines the minimum
duration of LFPS driven by Host Controller upon U2 exit LFPS handshake. Note that
there is an uncertainty of +-16us in actual duration driven by the Host Controller.
•
•
0b000 = 96us
•
0b001 = 160us
•
0b010 = 224us
•
0b011 = 288us
•
0b100 = 352us
•
0b101 = 416us
•
0b110 = 480us
•
0b111 = 544us
Power Well:
SUS
15
0b
RW
Max PING LFPS Rx Detection (XHCI_MAX_PING_LFPS):
This field defines the
maximum timing for PING LFPS. If an incoming LFPS will be considered a PING if it has
a timing such that it is less than or equal to the selected value. Otherwise it will be
considered for the other types of LFPS.
•
•
0b Max PING LFPS timing set to 256 ns
•
(32 link clocks)
•
1b Max PING LFPS timing set to 320 ns (40 link clocks)
Power Well:
SUSe
14:10
00h
RO
Reserved (RSVD_1):
Reserved.
Power Well:
Core
9:0
032h
RW
xHCI BESL to HIRD Distance (XHCI_BESL_HIRD_DT):
This field defines the gap
between BESL and duration of Resume signalling from Host upon Host Initiated Resume
from USB2.0 LPM. The default value of this register corresponds to xHCI spec defined
50us value.
•
•
Value BESL to HIRD Distance
•
000h = 0us
•
001h = 1us
•
002h = 2us
•
3FFh = 1023us
Power Well:
SUS
Bit
Range
Default &
Access
Field Name (ID): Description