Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2320
Datasheet
Default: 0040047Dh
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 0 1
DIS
_
SD
T_IDL_NR
RS
VD
XL
TR
TP
XL
TRE
PA
_
LT
V
USB2_PL0_L
TV
Bit
Range
Default &
Access
Field Name (ID): Description
31
0b
RW
Disable scheduler direct transition from IDLE to NO requirement
(DIS_SDT_IDL_NR):
•
•
0 = (default) allow scheduler direct transition from IDLE to NO requirement
•
1 = Disable scheduler direct transition from IDLE to NO requirement
Power Well:
Core
30:26
00h
RW
Reserved (RSVD):
Reserved.
Power Well:
Core
25
0b
RW
XHCI LTR Transition Policy (XLTRTP):
When '0', LTR messaging state machine
transitions from High, Medium, or Low LTR states to Active state upon the Alarm Timer
timout and stays in Active until the next service boundary. When '1', the LTR messaging
state machine transitions through High ? Med ? Low ? Active states assuming enough
latency is available for each transition.
Power Well:
Core
24
0b
RW
XHCI LTR Enable (XLTRE):
This bit must be set to enable LTV messaging from XHCI
to the PMC.
Power Well:
Core
23:12
400h
RW
Periodic Active LTV (PA_LTV):
•
•
23:22 Latency Scale
•
00b = Reserved
•
01b = Latency Value to be multiplied by 1024
•
10b = Latency Value to be multiplied by 32,768
•
11b = Latency Value to be multiplied by 1,048,576
•
•
21:12 Latency Value (ns) Defaults to 0 microseconds
Power Well:
Core