Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2323
18.7.184 xHC Latency Tolerance Parameters Low Idle Time Control
(XLTP_LITC)—Offset 8184h
Access Method
Default: 00000000h
Bit
Range
Default &
Access
Field Name (ID): Description
31:29
0h
RO
Reserved (RSVD):
Reserved.
Power Well:
Core
28:16
0000h
RW
Minimum Medium Idle Time (MMIT):
LTR value can be indicated. This value must be
larger than MIWL.
•
•
12:7 - Time value in # of 125 Microseconds Bus Intervals (0 - 8ms)
•
6:0 - Fractional BI Time value in Microseconds ( 0 - 124 Microseconds)
Power Well:
Core
15:13
0h
RO
Reserved (RSVD_1):
Reserved.
Power Well:
Core
12:0
0000h
RW
Medium Idle Wake Latency (MIWL):
This is the latency to access memory from the
Medium Idle Latency state. This value must be larger than LIWL.
•
•
12:7 - Time value in # of 125 Microseconds Bus Intervals (0 - 8ms)
•
6:0 - Fractional BI Time value in Microseconds ( 0 - 124 Microseconds)
Power Well:
Core
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RS
VD
MLIT
RS
VD_1
LIWL
Bit
Range
Default &
Access
Field Name (ID): Description
31:29
0h
RO
Reserved (RSVD):
Reserved.
Power Well:
Core
28:16
0000h
RW
Minimum Low Idle Time (MLIT):
LTR value can be indicated. This value must be
larger than LIWL
•
•
12:7 - Time value in # of 125 Microseconds Bus Intervals (0 - 8ms)
•
6:0 - Fractional BI Time value in Microseconds ( 0 - 124 Microseconds)
Power Well:
Core
15:13
0h
RO
Reserved (RSVD_1):
Reserved.
Power Well:
Core